Field of the Invention
The invention relates in general to a memory, and more particularly to reliability verification of a memory.
Description of the Related Art
In an application system adopting a memory, e.g., a multimedia system, due to the existence of interference from power lines and/or signal lines, test and analysis for power integrity (PI) and/or signal integrity (SI) need to be performed on the memory to verify the reliability of the memory. The above memory includes a dynamic random access memory (DRAM) and a synchronous dynamic random access memory (SDRAM). For example, for PI, when signals convert fast, the system reliability may be affected by power due to fluctuations in the power supply or ground level caused by cavity characteristics formed by resistance, voltage plane and ground plane. On the other hand, for SI, the system reliability may be affected by coupling, serial interference and mutual interference among signal transmission lines. For example, assume that a signal of only one signal line of the transmission lines changes from a low level to a high level, and signals of other multiple signal lines change from a high level to a low level. For this particular signal line, due to coupling, serial interference and mutual interference effects of the other multiple signals, signal characteristics of the signal line changed to the high level may become less satisfactory, including a low change speed to the high level or a reduced target voltage at the high level, such that the system reliability is degraded. Through the foregoing PI and/or SI analysis, the reliability of the system operating at the worst scenario, i.e., the worst signal mode, may be simulated. FIG. 1 shows a function block diagram of a conventional test data generating circuit. A memory test data generating circuit 120 accesses a memory 140 via a memory controller 130. A data bus between the memory test data generating circuit 120 and the memory controller 130 may be 256-bit or 128-bit, and a data bus between the memory controller 130 and the memory 140 may be 16-bit or 8-bit. When the memory is analyzed, the memory test data generating circuit 120 sends predetermined test data and associated test control signals for simulating worst noise. Such test data is written in and read from the memory 140 through the control of the memory controller 130, and the read data is analyzed to verify the reliability of the memory 140.
The predetermined test data needs to be significantly representative in order to analyze the memory 140. However, as shown in FIG. 1, there are different data bus bit widths between the memory data test generating circuit 120 and the memory controller 130, e.g., 256 bits and 128 bits, and different data bus bit widths between the memory controller 130 and the memory 140, e.g., 16 bits and 8 bits. Further, as shown in FIG. 2, in a situation where one memory controller 130 is coupled to two memories 140, the data bus bit widths between the memory controller 130 and the memories 140 are 32 bits. Due to such multiple different combinations of data bus bit widths, it is challenging for the memory test data generating circuit 120 to verify the reliability of the memory 140 using the same worst noise mode at the memory 140, hence resulting in increased memory test complications.